1. Field of the Invention
The invention relates to a flash memory controller and a flash memory access method, and more particularly to a flash memory controller and a flash memory access method capable of increasing a read and a program speed and reducing the error rate of a flash memory.
2. Description of the Related Art
NAND Flash is a non-volatile memory, thus maintaining data storage without power supply. Moreover, NAND flash has speedy program (i.e. write) and erase time. In a NAND flash, each memory cell occupies a relatively small chip area. Thus, a NAND flash has higher storage density than other memories.
Conventionally, a NAND flash memory may be grouped into single level cell (SLC) memory and multi level cell (MLC) memory, wherein the single level cell (SLC) memory may store one bit per cell, and the multi level cell (MLC) memory may store more than one bit per cell, for example, two bits per cell. As process technology advances, triple level cell (TLC) memory and quad level cell (QLC) memory devices have recently been proposed and developed to further increase the storage density of the flash memory, where the triple level cell (TLC) memory may store three bits per cell, and the quad level cell (QLC) memory may store four bits per cell.
The read or program operations of a flash memory are generally preformed in a page-wise (or called physical pages) fashion. Take a triple level cell (TLC) memory as an example; a physical page may be composed of a group of flash memory cells. Each flash memory cell may store three bits of data, including a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). The three bits may correspond to three different logical pages, therefore, the three bits may have different logical addresses for host addressing. In other words, for the TLC memory, one physical page may correspond to three logical pages. Therefore, take the TLC memory as an example; each physical page may be regarded as further comprising three sub-pages, and each sub-page may correspond to one of a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB) of the flash memory cell, respectively. Note that the sub-pages comprised by each physical page is a logical concept. Physically, it is not necessary for a flash memory cell to have the above-mentioned sub-pages.
With the increase in storage density, the read and program time increases, accordingly. Also, the data error rate increases as the amount of bits stored in each memory cell increases. Therefore, a novel design of a flash memory controller and a flash memory access method, which can increase a read and a program speed and further reduce the error rate of a flash memory, is highly required.